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| a/d converters - smt 1 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter functional diagram features ? 8-bit high speed single/ dual adc single channel mode: fsmax = 900 msps dual channel mode: fsmax = 450 msps ? integrated cross point switches (mux array) ? 1x to 50x digital gain no missing codes up to 32x ? 1x gain: 48.8 db snr. 10x gain: 48 db snr ? internal low jitter programmable clock divider ? ultra low power dissipation 650 mw including i/o at 900 msps ? 0.5 s start-up time from sleep, 15 s from power down ? internal reference circuitry with no external components required ? coarse and fine gain control ? digital fine gain adjustment for each adc typical applications ? point-to-point microwave links ? digital oscilloscopes ? satellite receivers figure 1. functional block diagram ? internal offset correction ? 1.8v supply voltage ? 1.7 - 3.6v cmos logic on control interface pins ? serial lvds/rsds output ? 7x7 mm qfn 48 (lp7d) package related products ? HMCAD1512 is pin compatible with hmcad1520 and hmcad1511 ? hmcad1511 is similar functionality as the HMCAD1512 with quad channel option and higher speed. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
a/d converters - smt 2 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter general description the HMCAD1512 is a versatile high performance low power analog-to-digital converter (adc), utilizing time-interleaving to increase sampling rate. integrated cross point switches activate the input selected by the user. the device contains 2 adcs that can be interleaved by the user to act as a single channel or two channels. in single channel mode, either of the two inputs can be selected as a valid input to the single adc channel. in dual channel mode, either of the two inputs can be selected for each adc channel. (the HMCAD1512 does not support the quad- channel mode. the hmcad1511 should be used for this purpose). an internal, low jitter and programmable clock divider makes it possible to use a single clock source for all operational modes. the HMCAD1512 is based on a proprietary structure, and employs internal reference circuitry, a serial control interface and serial lvds/rsds output data. data and frame synchronization clocks are supplied for data capture at the receiver. internal 1 to 50x digital coarse gain with enob > 7.5 up to 16x gain, allows digital implementation of oscilloscope gain settings. internal digital fne gain can be set separately for each adc to calibrate for gain errors. various modes and confguration settings can be applied to the adc through the serial control interface (spi). each channel can be powered down independently and data format can be selected through this interface. a full chip idle mode can be set by a single external pin. register settings determine the exact function of this pin. HMCAD1512 is designed to easily interface with field programmable gate arrays (fpgas) from several vendors. electrical specifcations dc specifcations avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, fs = 250 msps, dual channel mode, 50% clock duty cycle, -1 dbfs 70 mhz input signal, 1x/0 db digital gain (fne and coarse), unless otherwise noted parameter description min typ max unit dc accuracy no missing codes guaranteed offset offset error after internal digital offset correction 0.05 lsb g abs gain error 6 %fs g rel gain matching between channels. 3 sigma value at worst case conditions 0.5 %fs dnl differential non linearity 0.2 lsb inl integral non linearity 0.5 lsb v cm,out common mode voltage output v avdd /2 analog input v cm,in analog input common mode voltage v cm - 0.1 v cm +0.2 v fsr differential input voltage full scale range 2 vpp c in,d differential input capacitance, dual channel mode 7 pf c in,s differential input capacitance, single channel mode 11 pf power supply v avdd analog supply voltage 1.7 1.8 2 v v dvdd digital and output driver supply voltage 1.7 1.8 2 v v ovdd digital cmos input supply voltage 1.7 1.8 3.6 v temperature t a operating free-air temperature -40 85 c for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 3 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter ac specifcations avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 50% clock duty cycle, -1 dbfs 71 mhz input signal, gain = 1x, rsds output data levels unless otherwise noted parameter description min typ max unit performance snr signal to noise ratio, excluding interleaving spurs single ch mode, f s = 900 msps 47. 5 48.8 dbfs single ch mode, f s = 900 msps, f in = 170 mhz 48.5 dbfs single ch mode, f s = 900 msps, gain = 10x 48 dbfs dual ch mode, f s = 450 msps 48 49 dbfs sinad incl signal to noise and distortion ratio, including interleaving spurs single ch mode, f s = 900 msps 44.8 dbfs dual ch mode, f s = 450 msps 43.5 dbfs sinad excl signal to noise and distortion ratio, excluding interleaving spurs single ch mode, f s = 900 msps 47 48.3 dbfs single ch mode, f s = 900 msps, f in = 170 mhz 46.5 dbfs single ch mode, f s = 900 msps, gain = 10x 47. 3 dbfs dual ch mode, f s = 450 msps 47. 5 48.3 dbfs sfdr incl spurious free dynamic range, including interleaving spurs single ch mode, f s = 900 msps 49 dbc dual ch mode, f s = 450 msps 44 dbc sfdr excl spurious free dynamic range, excluding interleaving spurs single ch mode, f s = 900 msps 55 64 dbc single ch mode, f s = 900 msps, f in = 170 mhz 63 dbc single ch mode, f s = 900 msps, gain = 10x 62 dbc dual ch mode, f s = 450 msps 55 63 dbc hd2/3 worst of hd2/hd3 single ch mode, f s = 900 msps 60 65 dbc single ch mode, f s = 900 msps, f in = 170 mhz 65 dbc single ch mode, f s = 900 msps, gain = 10x 63 dbc dual ch mode, f s = 450 msps 57 63 dbc enob excl effective number of bits, excluding interleaving spurs single ch mode, f s = 900 msps 7.7 bits single ch mode, f s = 900 msps, f in = 170 mhz 7.4 bits single ch mode, f s = 900 msps, gain = 10x 7. 5 bits dual ch mode, f s = 450 msps 7.7 bits x tlk,2 crosstalk dual ch mode. signal applied to 1 channel (f in0 ). measurement taken on one channel with full scale at f in1 . f in1 = 71 mhz, f in0 = 70 mhz -90 dbc power supply single ch: f s = 900 ms/s, dual ch: f s = 450 ms/s i avdd analog supply current 250 ma i dvdd digital and output driver supply current 112 ma p avdd analog power 450 mw p dvdd digital power 200 mw p tot total power dissipation 650 mw p pd power down mode dissipation 15 w p slp deep sleep mode power dissipation 72 mw p slpch power dissipation with all channels in sleep channel mode (light sleep) 153 mw p slpch_sav power dissipation savings per channel off (duel channel mode) 248 mw for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 4 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter ac specifcations avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, 50% clock duty cycle, -1 dbfs 71 mhz input signal, gain = 1x, rsds output data levels unless otherwise noted parameter description min typ max unit analog input fpbw full power bandwidth 650 mhz clock inputs f smax max. conversion rate in modes: single ch 900 /450 msps dual ch f smin min. conversion rate in modes: single ch 120 / msps dual ch 60 / digital and switching specifcations avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, rsds output data levels, unless otherwise noted parameter description min typ max unit clock inputs dc duty cycle 45 55 % high compliance lvds supported up to 700 mhz lvpecl, sine wave, cmos, lvds v ck,sine differential input voltage swing, sine wave clock input 1500 mvpp v ck,cmos voltage input range cmos (clkn connected to ground) v ovdd v cm,ck input common mode voltage. keep voltages within ground and voltage of ovdd 0.3 v ovdd -0.3 v c ck differential input capacitance 3 pf logic inputs (cmos) v hi high level input voltage. v ovdd 3.0v 2 v v hi high level input voltage. v ovdd = 1.7v C 3.0v 0.8 v ovdd v v li low level input voltage. v ovdd 3.0v 0 0.8 v v li low level input voltage. v ovdd = 1.7v C 3.0v 0 0.2 v ovdd v i hi high level input leakage current +/-10 a i li low level input leakage current +/-10 a c i input capacitance 3 pf data outputs compliance lvds / rsds v out differential output voltage, lvds 350 mv v out differential output voltage, rsds 150 mv v cm output common mode voltage 1. 2 v output coding default/optional offset binary/ 2s complement timing characteristics t a aperture delay 1. 5 ns t j aperture jitter, one bit set to 1 in jitter_ctrl<7:0> 160 fsrms t skew timing skew between adc channels 2.5 psrms t su start up time from power down mode and deep sleep mode to active mode in s. see section clock frequency for details. 15 s t slpch start up time from sleep channel mode to active mode s t ovr out of range recovery time 1 clock cycles t lathsmd pipeline delay, dual channel mode 64 clock cycles t lathsms pipeline delay, single channel mode 128 clock cycles for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 5 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter digital and switching specifcations avdd = 1.8v, dvdd = 1.8v, ovdd = 1.8v, rsds output data levels, unless otherwise noted parameter description min typ max unit lvds output timing characteristics t data lclk to data delay time (excluding programmable phase shift) 50 ps t prop clock propagation delay. 6*t lvds +2.2 7*t lvds +3.5 7*t lvds +5.0 ns lvds bit-clock duty-cycle 45 55 % lclk cycle frame clock cycle-to-cycle jitter 2.5 % lclk cycle t edge data rise- and fall time 20% to 80% 0.7 ns t clkedge clock rise- and fall time 20% to 80% 0.7 ns table 1: maximum voltage ratings pin reference pin rating avdd avss -0.3v to +2.3v dvdd dvss -0.3v to +2.3v ovdd avss -0.3v to +3.9v avss / dvss dvss / avss -0.3v to +0.3v analog inputs and outputs avss -0.3v to +2.3v clkx avss -0.3v to +3.9v lvds outputs dvss -0.3v to +2.3v digital inputs dvss -0.3v to +3.9v applying voltages to the pins beyond those specifed in table 1 could cause permanent damage to the circuit. table 2: maximum temperature ratings operating temperature -40 to +85 c storage temperature -60 to +150 c maximum junction temperature 110 c thermal resistance (rth) 29 c/w soldering profle qualifcation j-std-020 esd sensivity hbm class 1c esd sensivity cdm class iii electrostatic sensitive device observe handling precautions stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 6 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter pin confguration and description figure 2: package diagram table 3: pin descriptions pin name description pin number # of pins avdd analog power supply, 1.8v 1, 36 2 csn chip select enable. active low 2 1 sdata serial data input 3 1 sclk serial clock input 4 1 resetn reset spi interface. active low 5 1 pd power-down input. activate after applying power in order to initialize the adc correctly. alternatively use the spi power down feature 6 1 dvdd digital and i/o power supply, 1.8v 7, 3 0 2 dvss digital ground 8, 29 2 dp1a lvds channel 1a, positive output 9 1 dn1a lvds channel 1a, negative output 10 1 dp1b lvds channel 1b, positive output 11 1 dn1b lvds channel 1b, negative output 12 1 dp2a lvds channel 2a, positive output 13 1 dn2a lvds channel 2a, negative output 14 1 dp2b lvds channel 2b, positive output 15 1 dn2b lvds channel 2b, negative output 16 1 lclkp lvds bit clock, positive output 17 1 lclkn lvds bit clock, negative output 18 1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 7 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 3: pin descriptions pin name description pin number # of pins fclkp lvds frame clock (1x), positive output 19 1 fclkn lvds frame clock (1x), negative output 20 1 dp3a lvds channel 3a, positive output 21 1 dn3a lvds channel 3a, negative output 22 1 dp3b lvds channel 3b, positive output 23 1 dn3b lvds channel 3b, negative output 24 1 dp4a lvds channel 4a, positive output 25 1 dn4a lvds channel 4a, negative output 26 1 dp4b lvds channel 4b, positive output 27 1 dn4b lvds channel 4b, negative output 28 1 avss2 analog ground domain 2 31 1 avdd2 analog power supply domain 2, 1.8v 32 1 ovdd digital cmos inputs supply voltage 33 1 clkn negative differential input clock. 34 1 clkp positive differential input clock 35 1 avss analog ground 39, 40, 41, 42, 43, 44, 45 7 in2 negative differential input signal, channel 2 37 1 ip2 positive differential input signal, channel 2 38 1 in1 negative differential input signal, channel 1 46 1 ip1 positive differential input signal, channel 1 47 1 vcm common mode output pin, 0.5*avdd 48 1 start up initialization as part of the HMCAD1512 power-on sequence both a reset and a power down cycle have to be applied to ensure correct start-up initialization. make sure that the supply voltages are properly settled before the start up initialization is being performed. reset can be done in one of two ways: 1. by applying a low-going pulse (minimum 20 ns) on the resetn pin (asynchronous). 2. by using the serial interface to set the rst bit high. internal registers are reset to default values when this bit is set. the rst bit is self-reset to zero. when using this method, do not apply any low-going pulse on the resetn pin. power down cycling can be done in one of two ways: 1. by applying a high-going pulse (minimum 20 ns) on the pd pin (asynchronous). 2. by cycling the pd bit in register 0fhex to high (reg value 0200hex) and then low (reg value 0000hex). important: the operating mode must be selected (dual channel or single channel) in register 0x31 after power-up, reset and/or power cycling. serial interface for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 8 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter the HMCAD1512 confguration registers can be accessed through a serial interface formed by the input-only pins sdata (serial interface data), sclk (serial interface clock) and csn (chip select, active low). the following occurs when csn is set low: ? serial data are shifted into the chip ? at every rising edge of sclk, the value present at sdata is latched ? sdata is loaded into the register every 24th rising edge of sclk multiples of 24-bit words data can be loaded within a single active csn pulse. if more than 24 bits are loaded into sdata during one active csn pulse, only the frst 24 bits are kept. the excess bits are ignored. every 24-bit word is divided into two parts: ? the frst eight bits form the register address ? the remaining 16 bits form the register data acceptable sclk frequencies are from 20mhz down to a few hertz. duty-cycle does not have to be tightly controlled. timing diagram figure 4 shows the timing of the serial port interface. table 4 explains the timing variables used in fgure 4. c s n s c l k s d a t a t s t h t c s t c h i t h i t l o t c k t c h a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 1 5 d 1 4 d 1 3 d 1 2 d 1 1 d 1 0 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 figure 3: serial port interface timing table 4: serial port interface timing defnitions parameter description minimum value unit t cs setup time between csn and sclk 8 ns t ch hold time between csn and sclk 8 ns t hi sclk high time 20 ns t lo sclk low time 20 ns t ck sclk period 50 ns t s data setup time 5 ns t h data hold time 5 ns timing diagrams for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 9 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter t l vd s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n nnnn n n n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n + 6 4 n+68 a n alog input inp u t c l o c k lclk p l c lk n f c lk p f cl k n n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 t pr o p d 2 d 3 d 4 d 5 d 6 d 7 n+66 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 d 2 d 3 d 4 d 5 d 6 d 7 n+62 n+70 n+63 n+65 n+67 n + 6 9 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 d 2 d 3 d 4 d 5 d 6 d 7 dx 1a / dx 3a dx 1 b / dx 3 b dx 2a / dx 4a dx 2 b / dx 4 b figure 4: dual channel - lvds timing 8-bit output for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 10 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter t l vd s d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n nnnn n n n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n - 8 n+128 n+136 a n alog input inp u t c l o c k lclk p l c lk n f c lk p f cl k n d x 1 a t pr o p d 2 d 3 d 4 d 5 d 6 d 7 n+132 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n + 1 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 n - 7 dx 1b d 2 d 3 d 4 d 5 d 6 d 7 n+12 4 n+14 0 n+126 n + 1 30 n + 1 34 n+138 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n + 2 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 n - 6 d x 2 a d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n + 3 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 n - 5 dx 2b d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 n - 4 dx 3a d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n + 5 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 n - 3 d x 3 b d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n + 6 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 dx 4a n - 1 0 n - 1 0 n - 1 0 n - 1 0 n - 1 0 n - 1 0 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n + 7 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 n - 1 d x 4 b n - 9 n - 9 n - 9 n - 9 n - 9 n - 9 d 2 d 3 d 4 d 5 d 6 d 7 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n + 4 n - 1 1 n - 1 1 n - 1 1 n - 1 1 n - 1 1 n - 1 1 n - 1 2 n - 1 2 n - 1 2 n - 1 2 n - 1 2 n - 1 2 n - 1 4 n - 1 4 n - 1 4 n - 1 4 n - 1 4 n - 1 4 n - 1 3 n - 1 3 n - 1 3 n - 1 3 n - 1 3 n - 1 3 n - 1 5 n - 1 5 n - 1 5 n - 1 5 n - 1 5 n - 1 5 n - 1 6 n - 1 6 n - 1 6 n - 1 6 n - 1 6 n - 1 6 figure 5: single channel - lvds timing 8-bit output t l v d s t l v d s /2 dx x x t dat a lclk p lclk n figure 6: lvds data timing for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 11 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter register map summary table 5: register map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst * self-clearing software reset. inactive x 0x00 sleep2_ch <2:1> channel-specifc sleep mode for a dual channel setup. inactive x x 0x0f sleep1_ch1 channel-specifc sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg <1:0> confgures the pd pin function. pd pin confgured for power-down mode x x ilvds_lclk <2:0> lvds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame <2:0> lvds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat <2:0> lvds current drive programmability for output data pins. 3.5 ma drive x x x term_dat <2:0> programmable termination for output data buffers. termination disabled 1 x x x invert2_ch <2:1> channel specifc swapping of the analog input signal for a dual channel setup. ipx is positive input x x 0x24 invert1_ch1 channel specifc swapping of the analog input signal for a single channel setup. ipx is positive input x en_ramp enables a repeating full-scale ramp pattern on the outputs. inactive x 0 0 0x25 custom_pat enable the mode wherein the output toggles between two defned codes. inactive 0 x 0 bits_custom1 <7:0> bits for the single custom pattern and for the frst code of the dual custom pattern. 0x00 x x x x x x x x 0x26 bits_custom2 <7:0> bits for the second code of the dual custom pattern. 0x00 x x x x x x x x 0x27 cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 in a dual channel setup. 1x gain x x x x cgain1_ch1 <3:0> programmable coarse gain channel 1 in a single channel setup. 1x gain x x x x jitter_ctrl <7:0> clock jitter adjustment. 160 fsrms x x x x x x x x 0x30 channel_ num <2:0> * set number of channels: 1, or 2 channels. 4 channels x x x 0x31 clk_divide <1:0>* defne clock divider factor: 1, 2, 4 divide by 1 x x coarse_ gain_cfg confgures the coarse gain setting x-gain enabled x 0x33 fne_gain_en enable use of fne gain. disabled x fgain_ branch1 <6:0> programmable fne gain for branch1. 0db gain x x x x x x x 0x34 fgain_ branch2 <6:0> programmable fne gain for branch 2. 0db gain x x x x x x x fgain_ branch3 <6:0> programmable fne gain for branch 3. 0db gain x x x x x x x 0x35 fgain_ branch4 <6:0> programmable fne gain for branch 4. 0db gain x x x x x x x for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 12 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 5: register map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address fgain_ branch5 <6:0> programmable fne gain for branch 5. 0db gain x x x x x x x 0x36 fgain_ branch6 <6:0> programmable fne gain for branch 6. 0db gain x x x x x x x fgain_ branch7 <6:0> programmable fne gain for branch 7. 0db gain x x x x x x x 0x37 fgain_ branch8 <6:0> programmable fne gain for branch 8. 0db gain x x x x x x x inp_sel_adc1 <4:0> input select for adc 1. signal input: ip1/in1 x x x x 0 0x3a inp_sel_adc2 <4:0> input select for adc 2. signal input: avss x x x x 0 inp_sel_adc3 <4:0> input select for adc 3. signal input: avss x x x x 0 0x3b inp_sel_ adc4<4:0> input select for adc 4. signal input: ip2/ in2 x x x x 0 phase_ddr <1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 btc_mode binary twos complement format for adc output data. straight offset binary x 0x46 msb_frst serialized adc output data comes out with msb frst. lsb frst x adc_curr <2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc <1:0> vcm buffer driving strength control. nominal x x lvds_pd_ mode controls lvds power down mode high z-mode x 0x52 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 13 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 5: register map name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address low_clk_ freq * low clock frequency used. inactive x 0 0 0 0x53 lvds_ advance advance lvds data bits and frame clock by one clock cycle inactive 0 x 0 0 0 lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 0 0 0 fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 startup_ctrl <2:0> * controls start-up time. 000 x x x 0x56 undefned register addresses must not be written to; incorrect behavior may be the result. unused register bits (blank table cells) must be set to 0 when programming the registers. all registers can be written to while the chip is in power down mode. * these registers require a power down cycle when written to (see start up initialization). register description software reset name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address rst self-clearing software reset. inactive x 0x00 setting the rst register bit to 1, restores the default value of all the internal registers including the rst register bit itself. modes of operation and clock divide factor name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address channel_ num <1:0> set number of channels: 1or 2 channels. 4 channels x x x 0x31 clk_divide <1:0> defne clock divider factor: 1, 2, or 4 divide by 1 x x the HMCAD1512 has three main operating modes controlled by the register bits channel_num<2:0> as defned in table 6. power down mode, as described in section startup initialization, must be activated after or during a change of operating mode to ensure correct operation. all active operating modes utilize interleaving to achieve high sampling speed. dual channel mode interleaves 2 adcs each, while single channel mode interleaves all 4 adcs. table 6: modes of operation channel_num <2:0> mode of operation description 0 0 1 single channel single channel by interleaving adc1 to adc4 0 1 0 dual channel dual channel where channel 1 is made by interleaving adc1 and adc2, channel 2 by interleaving adc3 and adc4 1 0 0 quad channel mode not supported on HMCAD1512. only one of the 3bits should be activated at the same time. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 14 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter clk_divide<1:0> allows the user to apply an input clock frequency higher than the sampling rate. the clock divider will divide the input clock frequency by a factor of 1, 2, 4 defned by the clk_divide<1:0> register. by setting the clk_divide<1:0> value relative to the channel_num<2:0> value, the same input clock frequency can be used for all set - tings on number of channels. e.g: when increasing the number of channels from 1 to 2, the maximum sampling rate is reduced by a factor of 2. by letting clk_divide<1:0> follow the channel_num<2:0> value, and changing it from 1 to 2, the internal clock divider will provide the reduction of the sampling rate without changing the input clock frequency. table 7: clock divider factor clk_divide<1:0> clock divider factor sampling rate (fs) 00 (default) 1 input clock frequency / 1 01 2 input clock frequency / 2 10 4 input clock frequency / 4 11 n/a do not use input select name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address inp_sel_adc1 <4:0> input select for adc 1. signal input: ip1/in1 x x x x 0 0x3a inp_sel_adc2 <4:0> input select for adc 2. signal input: avss x x x x 0 inp_sel_adc3 <4:0> input select for adc 3. signal input: avss x x x x 0 0x3b inp_sel_adc4 <4:0> input select for adc 4. signal input: ip2/in2 x x x x 0 each adc is connected to the two input signals via a full fexible cross point switch, set up by inp_sel_adcx. in single channel mode, any one of the two inputs can be selected as valid input to the single adc channel. in dual channel mode, either of the two inputs can be selected to each adc channel. the switching of inputs can be done during normal operation, and no additional actions are needed. the switching will occur instantaneously at the end of each spi command. table 8: select inp_sel_adcx<4:0> selected input 0001 0 ip1/in1 0010 0 avss (pins 43, 44) 0100 0 avss (pins 40, 41) 1000 0 ip2/in2 other do not use on the HMCAD1512, if the dual-channel mode is selected in register 0x31, the input selection for adc1 and adc2 must be: 00010 (i.e., ip1/in1); the input selection for adc3 and adc4 must be: 10000 (i.e., ip2/in2). in the single- channel mode, the input selection for all adcs may be either 00010 (i.e., ip1/in1) or 10000 (i.e., ip2/in2). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 15 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter figure 8: adc input signals through cross point switch full-scale control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address fs_cntrl <5:0> fine adjust adc full scale range 0% change x x x x x x 0x55 the full-scale voltage range of HMCAD1512 can be adjusted using an internal 6-bit dac controlled by the fs_cntrl register. changing the value in the register by one step, adjusts the full-scale range by approximately 0.3%. this leads to a maximum range of 10% adjustment. table 9 shows how the register settings correspond to the full-scale range. note that the values for full-scale range adjustment are approximate. the dac is, however, guaranteed to be monotonous. the full-scale control and the programmable gain features differ in two major ways: 1. the full-scale control feature controls the full-scale voltage range in an analog fashion, whereas the programmable gain is a digital feature. 2. the programmable gain feature has much coarser gain steps and larger range than the full-scale control. table 9: register values with corresponding change in full-scale range fs_cntrl<5:0> full-scale range adjustment 111111 9.70% 111110 9.40% 100001 0.30% 100000 0% 011111 - 0.3% 000001 - 9.7% 000000 - 10% for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 16 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter current control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address adc_curr<2:0> adc current scaling. nominal x x x 0x50 ext_vcm_bc<1:0> vcm buffer driving strength control. nominal x x there are two registers that impact performance and power dissipation. the adc_curr register scales the current consumption in the adc core. the performance is guaranteed at the nomi - nal setting. lower power consumption can be achieved by reducing the adc_curr value, see table 10. the impact on performance is low for settings down to minimum, but will depend on the adc sampling rate. table 10: adc current control settings adc_curr<2:0> adc core current 100 -40% (lower performance) 101 -30% 110 -20% 111 -10% 000 (default) nominal 001 do not use 010 do not use 011 do not use the ext_vcm_bc register controls the driving strength in the buffer supplying the voltage on the vcm pin. if this pin is not in use, the buffer can be switched off. if current is drawn from the vcm pin, the driving strength can be increased to keep the voltage on this pin at the correct level. table 11: external common mode voltage buffer driving strength ext_vcm_bc<1:0> vcm buffer driving strength (a) max current sinked/sourced from vcm pin with < 20 mv voltage change. 00 off (vcm foating) 01 (default) 20 10 400 11 700 start-up and clock jitter control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address startup_ctrl<2:0> controls start-up time. '000' x x x 0x56 jitter_ctrl<7:0> clock jitter adjustment. 160 fsrms x x x x x x x x 0x30 to optimize start up time, a register is provided where the start-up time in number of clock cycles can be set. some internal circuitry have start up times that are clock frequency independent. default counter values are set to accom - modate these start up times at the maximum clock frequency (sampling rate). this will lead to increased start up times at low clock frequencies. setting the value of this register to the nearest higher clock frequency will reduce the count values of the internal counters, to better ft the actual start up time, such that the start up time will be reduced. the start up times from power down and sleep modes are changed by this register setting. if the clock divider is used (set to other than 1), the input clock frequency must be divided by the divider factor to fnd the correct clock frequency range (see table 7). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 17 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 12: start-up time control settings single channel dual channel startup_ctrl <2:0> clock frequency range (msps) startup delay (clock cycles) startup delay (s) startup_ctrl <2:0> clock frequency range (msps) startup delay (clock cycles) startup delay (s) 100 640 - 900 12288 12.3 - 19.2 100 320 - 450 6144 12.3 - 19.2 000 400 - 640 7936 12.4 - 19.8 000 200 - 320 3968 12.4 - 19.8 001 260 - 400 5120 12.8 - 19.7 001 130 C 200 2560 12.8 - 19.7 101 160 - 260 3360 12.9 - 21 101 80 - 130 1680 12.9 - 21 011 120 - 160 2080 13 - 17.3 011 60 C 80 1040 13 - 17.3 other do not use - - other do not use - - jitter_ctrl<7:0> allows the user to set a trade-off between power consumption and clock jitter. if all bits in the register is set low, the clock signal is stopped. the clock jitter depends on the number of bits set to 1 in the jitter_ctrl<7:0> register. which bits are set high does not affect the result. table 13: clock jitter performance number of bits to '1' in jitter_ctrl<7:0> clock jitter performance (fsrms) module current consumption (ma) 1 160 1 2 150 2 3 136 3 4 130 4 5 126 5 6 124 6 7 122 7 8 120 8 0 clock stopped for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 18 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter lvds output confguration and control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address low_clk_freq low clock frequency used. inactive x 0 0 0 0x53 lvds_advance advance lvds data bits and frame clock by one clock cycle inactive 0 x 0 0 0 lvds_delay delay lvds data bits and frame clock by one clock cycle inactive x 0 0 0 0 phase_ddr<1:0> controls the phase of the lclk output relative to data. 90 degrees x x 0x42 btc_mode binary two's complement format for adc output data. straight offset binary x 0x46 msb_frst serialized adc output data comes out with msb frst. lsb frst x the HMCAD1512 uses an 8-bit serial lvds output interface as shown in the timing diagrams section. the different selection of number of channels uses the lvds outputs as defned by table 14. table 14: use of lvds outputs channel set-up lvds outputs used single channel d1a, d1b, d2a, d2b, d3a, d3b, d4a, d4b dual channel, channel 1 d1a, d1b, d2a, d2b dual channel, channel 2 d3a, d3b, d4a, d4b maximum data output bit-rate for HMCAD1512 is 900 mbps. the maximum sampling rate for the different confgura - tions is given by table 15. the sampling rate is set by the frequency of the input clock (fs). the frame-rate, i.e. the frequency of the fclk signal on the lvds outputs, depends on the selected mode and the sampling frequency (fs) as defned in table 16. table 15: maximum sampling rate for different HMCAD1512 confgurations product single channel (msps) dual channel (msps) HMCAD1512 900 450 table 16: output data frame rate mode of operation frame-rate (fclk frequency) single channel f s / 8 dual channel f s / 4 if the HMCAD1512 device is used at a low sampling rate the register bit low_clk_freq has to be set to 1. see table 17 for when to use this register bit for the different modes of operation. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 19 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 17: use of register bit low_clk_freq mode of operation limit when low_clk_freq should be activated single channel f s < 240 mhz dual channel f s < 120 mhz quad channel f s < 60 mhz to ease timing in the receiver when using multiple HMCAD1512, the device has the option to adjust the timing of the output data and the frame clock. the propagation delay with respect to the adc input clock can be moved one lvds clock cycle forward or backward, by using lvds_delay and lvds_advance, respectively. see fgure 10 for details. note that lclk is not affected by lvds_delay or lvds_advance settings. d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 n n nnn n n n - 4 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 i np u t c l o c k lclk p l c lk n f clk n f clk p dx x x d 0 d 1 d 2 d 3 d 4 d 5 nnnn n n n - 4 n - 4 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 f clk p f clk n dx x x d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 nnnn n n n n n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 n - 2 f cl k p f clk n dx x x l v d s_dela y = ' 1 ' : l v d s_a d v a n c e = ' 1 ' : default : t l vd s d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t l vd s t l vd s t pr o p t pr o p t pr o p figure 9: lvds output timing adjustment the lvds output interface of HMCAD1512 is a ddr interface. the default setting is with the lclk rising and falling edge transitions in the middle of alternate data windows. the phase for lclk can be programmed relative to the output frame clock and data bits using phase_ddr<1:0>. the lclk phase modes are shown in fgure 11. the default timing is identical to setting phase_ddr<1:0>=10. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 20 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter f cl k n f cl k p lclk p lcl k n dx x < 1: 0> f cl k n f cl k p lclk p lclk n dx x < 1: 0> f clk n f clk p lclk p lclk n d x x < 1 :0 > f clk n f clk p l cl k p lclk n d x x < 1 :0 > p hase _ ddr<1: 0>='00' (270 deg) p hase _ ddr<1: 0>='10' (90 deg) p hase _ ddr<1: 0>='01' (180 deg) p ha s e _ddr< 1 : 0 > =' 1 1 ' ( 0 de g ) figure 10: phase programmability modes for lclk the default data output format is offset binary. twos complement mode can be selected by setting the btc_mode bit to 1 which inverts the msb. the frst bit of the frame (following the rising edge of fclkp) is the lsb of the adc output for default settings. pro - gramming the msb_frst mode results in reverse bit order, and the msb is output as the frst bit following the fclkp rising edge. lvds drive strength programmability name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address ilvds_lclk <2:0> lvds current drive programmability for lclkp and lclkn pins. 3.5 ma drive x x x 0x11 ilvds_frame <2:0> lvds current drive programmability for fclkp and fclkn pins. 3.5 ma drive x x x ilvds_dat <2:0> lvds current drive programmability for output data pins. 3.5 ma drive x x x the current delivered by the lvds output drivers can be confgured as shown in table 18. the default current is 3.5ma, which is what the lvds standard specifes. to reduce power consumption in the HMCAD1512, reduced swing data signaling (rsds), is recommended. the output current drive setting should then be 1.5 ma. setting the ilvds_lclk<2:0> register controls the current drive strength of the lvds clock output on the lclkp and lclkn pins. setting the ilvds_frame<2:0> register controls the current drive strength of the frame clock output on the fclkp and fclkn pins. setting the ilvds_dat<2:0> register controls the current drive strength of the data outputs on the d[8:1]p and d[8:1]n pins. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 21 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 18: lvds output drive strength for lclk, fclk & data ilvds_*<2:0> lvds drive strength 000 3.5 ma (default) 001 2.5 ma 101 1.5 ma (rsds) 011 0.5 ma 100 7.5 ma 101 6.5 ma 110 5.5 ma 111 4.5 ma power mode control name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address sleep2_ch <2:1> channel-specifc sleep mode for a dual channel setup. inactive x x 0x0f sleep1_ch1 channel-specifc sleep mode for a single channel setup. inactive x sleep go to sleep-mode. inactive x pd go to power-down. inactive x pd_pin_cfg <1:0> confgures the pd pin function. pd pin confgured for power-down mode x x lvds_pd_mode controls lvds power down mode high z-mode x 0x52 the HMCAD1512 device has several modes for power management, from sleep modes with short start up time to full power down with extremely low power dissipation. there are two sleep modes, both with the lvds clocks (fclk, lclk) running, such that the synchronization with the receiver is maintained. the frst is a light sleep mode (sleep*_ ch) with short start up time, and the second a deep sleep mode (sleep) with the same start up time as full power down. setting sleep2_ch a/d converters - smt 22 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter programmable gain name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address cgain_cfg confgures the coarse gain setting x-gain enabled x 0x33 fne_gain_en enable use of fne gain. disabled x cgain2_ch1 <3:0> programmable coarse gain channel 1 in a dual channel setup. 1x gain x x x x 0x2b cgain2_ch2 <3:0> programmable coarse gain channel 2 in a dual channel setup. 1x gain x x x x cgain1_ch1 <3:0> programmable coarse gain channel 1 in a 1 channel setup. 1x gain x x x x fgain_branch1<6:0> programmable fne gain for branch1. 0db gain x x x x x x x 0x34 fgain_branch2<6:0> programmable fne gain for branch 2. 0db gain x x x x x x x fgain_branch3<6:0> programmable fne gain for branch 3. 0db gain x x x x x x x 0x35 fgain_branch4<6:0> programmable fne gain for branch 4. 0db gain x x x x x x x fgain_branch5<6:0> programmable fne gain for branch 5. 0db gain x x x x x x x 0x36 fgain_branch6<6:0> programmable fne gain for branch 6. 0db gain x x x x x x x fgain_branch7<6:0> programmable fne gain for branch 7. 0db gain x x x x x x x 0x37 fgain_branch8<6:0> programmable fne gain for branch 8. 0db gain x x x x x x x the device includes a digital programmable gain in addition to the full-scale control. the programmable gain of each channel can be individually set using a four bit code, indicated as cgain*<3:0>. the gain is confgured by the register cgain_cfg, when cgain_cfg equals 0 a gain in db steps is enabled as defned in table 20 otherwise if cgain_cfg equals 1 the gain is defned by table 21. there will be no missing codes for gain settings lower than 32x (30db), due to higher than 8 bit resolution internally. table 19: gain setting C db step cgain_cfg cgain*<3:0> implemented gain (db) 0 0000 0 0 0001 1 0 0010 2 0 0 011 3 0 0100 4 0 0101 5 0 0110 6 0 0111 7 0 1000 8 0 1001 9 0 1010 10 0 1011 11 0 110 0 12 0 1101 not used 0 1110 not used 0 1111 not used for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 23 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 20: gain setting C x step cgain_cfg cgain*<3:0> implemented gain factor (x) 1 0000 1 1 0001 1.25 1 0010 2 1 0 011 2.5 1 0100 4 1 0101 5 1 0110 8 1 0111 10 1 1000 12.5 1 1001 16 1 1010 20 1 1011 25 1 110 0 32 1 1101 50 1 1110 not used 1 1111 not used there is a digital fne gain implemented for each adc to adjust the fne gain errors between the adcs. the gain is controlled by fgain_branch* as defned in table 22. there will be no missing codes when using digital fne gain, due to higher resolution internally. to enable the fne gain function the register bit fne_gain_en has to be activated, set to 1. table 21: fine gain setting fgain_branchx<6:0> arithmetic function implemented gain (x) gain (db) 0 1 1 1 1 1 1 out = (1 + 2 -8 + 2 -9 + 2- 10 + 2 - 11 + 2 -12 + 2 -13 ) * in 1.0077 0.0665 0 1 1 1 1 1 0 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 + 2 -12 ) * in 1.0076 0.0655 0 1 1 1 1 0 1 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 + 2 -13 ) * in 1.0074 0.0644 0 1 1 1 1 0 0 out = (1 + 2 -8 + 2 -9 + 2 -10 + 2 -11 ) * in 1.0073 0.0634 0 0 0 0 0 1 1 out = (1 + 2 -12 + 2 -13 ) * in 1.0004 0.0031 0 0 0 0 0 1 0 out = (1 + 2 -12 ) * in 1.0002 0.0021 0 0 0 0 0 0 1 out = (1 + 2 -13 ) * in 1.0001 0.001 0 0 0 0 0 0 0 out = in 1.0000 0.0000 1 1 1 1 1 1 1 out = in 1.0000 0.0000 1 1 1 1 1 1 0 out = (1 - 2 -13 ) * in 0.9999 - 0.0 011 1 1 1 1 1 0 1 out = (1 - 2 -12 ) * in 0.9998 -0.0021 1 1 1 1 1 0 0 out = (1 - 2 -12 - 2 -13 ) * in 0.9996 -0.0032 1 0 0 0 0 1 1 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 ) * in 0.9927 -0.0639 1 0 0 0 0 1 0 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 - 2 -13 ) * in 0.9926 -0.0649 1 0 0 0 0 0 1 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 -11 - 2 -12 ) * in 0.9924 -0.0660 1 0 0 0 0 0 0 out = (1 - 2 -8 - 2 -9 - 2 -10 - 2 - 11 - 2 -12 - 2 -13 ) * in 0.9923 -0.0670 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 24 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter analog input invert name description default d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 hex address invert2_ch <2:1> channel specifc swapping of the analog input signal for a dual channel setup. ipx is positive input x x 0x24 invert1_ch1 channel specifc swapping of the analog input signal for a 1 channel setup. ipx is positive input x the ipx pin represents the positive analog input pin, and inx represents the negative (complementary) input. setting the bits marked invertx_ch a/d converters - smt 25 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter theory of operation HMCAD1512 is a multi mode high-speed, cmos adc, consisting of 8 adc branches, confgured in different channel modes, using interleaving to achieve high speed sampling. for all practical purposes, the device can be considered to contain 4 adcs. fine gain is adjusted for each of the eight branches separately. HMCAD1512 utilizes a serial lvds output, described in register description, output confguration and control. the clocks needed (fclk, lclk) for the lvds interface are generated by an internal pll. the HMCAD1512 operate from one clock input, which can be differential or single ended. the sampling clocks for each of the four channels are generated from the clock input using a carefully matched clock buffer tree. internal clock dividers are utilized to con - trol the clock for each adc during interleaving. the clock tree is controlled by the mode of operations. HMCAD1512 uses internally generated references. the differential reference value is 1v. this results in a differential input of ?1v to correspond to the zero code of the adc, and a differential input of +1v to cor - respond to the full-scale code (code 255). the adc employs a pipeline converter architecture. each pipeline stage feeds its output data into the digi - tal error correction logic, ensuring excellent differential linearity and no missing codes. HMCAD1512 operates from two sets of supplies and grounds. the analog supply and ground set is identi - fed as avdd and avss, while the digital set is identi - fed by dvdd and dvss. interleaving effects and sampling order interleaving adcs will generate interleaving artifacts caused by gain, offset and timing mismatch between the adc branches. the design of HMCAD1512 has been optimized to minimize these effects. it is not possible, though, to eliminate mismatch completely, such that additional compensation may be needed, especially when using high digital gain settings. the internal digital fne gain control may be used to com - pensate for gain errors between the adc branches. due to the optimization of HMCAD1512 there is not a one-to-one correspondence between the sampling order, lvds output order and the branch number. tables 23, 24 and 25 give an overview of the corre - sponding branches, lvds outputs and sampling order for the different high speed modes. table 22: dual channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 3 3 d2a 2 4 d2b 4 2 1 d3a 5 2 d3b 7 3 d4a 6 4 d4b 8 table 23: single channel mode channel # sampling order lvds output fine gain branch 1 1 d1a 1 2 d1b 6 3 d2a 2 4 d2b 5 5 d3a 8 6 d3b 3 7 d4a 7 8 d4b 4 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 26 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter recommended usage analog input the analog input to HMCAD1512 adc is a switched capacitor track-and-hold amplifer optimized for differ - ential operation. operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specifed. the vcm pin provides a volt - age suitable as common mode voltage reference. the internal buffer for the vcm voltage can be switched off, and driving capabilities can be changed program - ming the ext_vcm_bc<1:0> register. figure 11: input confguration figure 12 shows a simplifed drawing of the input net - work. the signal source must have sufficiently low output impedance to charge the sampling capacitors within one clock cycle. a small external resistor (e.g. 22 ohm) in series with each input is recommended as it helps reducing transient currents and dampens ringing behavior. a small differential shunt capacitor at the chip side of the resistors may be used to provide dynamic charging currents and may improve perfor - mance. the resistors form a low pass flter with the capacitor, and values must therefore be determined by requirements for the application. dc-coupling figure 13 shows a recommended confguration for dc-coupling. note that the common mode input volt - age must be controlled according to specifed values. preferably, the cm_ext output should be used as ref - erence to set the common mode voltage. figure 12: dc coupled input the input amplifer could be inside a companion chip or it could be a dedicated amplifer. several suitable single ended to differential driver amplifers exist in the market. the system designer should make sure the specifcations of the selected amplifer is adequate for the total system, and that driving capabilities comply with HMCAD1512 input specifcations. detailed confguration and usage instructions must be found in the documentation of the selected driver, and the values given in fgure 13 must be adjusted accord - ing to the recommendations for the driver. ac-coupling figure 13: transformer coupled input a signal transformer or series capacitors can be used to make an ac-coupled input network. figure 14 shows a recommended confguration using a trans - former. make sure that a transformer with sufficient linearity is selected, and that the bandwidth of the transformer is appropriate. the bandwidth should preferably exceed the sampling rate of the adc sev - eral times. it is also important to minimize phase mis - match between the differential adc inputs for good hd2 performance. this type of transformer coupled input is the preferred confguration for high frequency signals as most differential amplifers do not have ade - quate performance at high frequencies. magnetic cou - pling between the transformers and pcb traces may impact channel crosstalk, and must hence be taken into account during pcb layout. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 27 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter if the input signal is traveling a long physical distance from the signal source to the transformer (for example a long cable), kick-backs from the adc will also travel along this distance. if these kick-backs are not termi - nated properly at the source side, they are refected and will add to the input signal at the adc input. this could reduce the adc performance. to avoid this effect, the source must effectively terminate the adc kick-backs, or the traveling distance should be very short. figure 14: ac coupled input figure 15 shows ac-coupling using capacitors. resis - tors from the cm_ext output, rcm, should be used to bias the differential input signals to the correct volt - age. the series capacitor, ci, form the high-pass pole with these resistors, and the values must therefore be determined based on the requirement to the high-pass cut-off frequency. note that start up time from sleep mode and power down mode will be affected by this flter as the time required to charge the series capacitors is dependent on the flter cut-off frequency. clock input and jitter considerations typically high-speed adcs use both clock edges to generate internal timing signals. in HMCAD1512 only the rising edge of the clock is used. the input clock can be supplied in a variety of for - mats. the clock pins are ac-coupled internally, hence a wide common mode voltage range is accepted. differential clock sources such as lvds, lvpecl or differential sine wave can be utilized. lvds/lvpecl clock signals must be appropriately terminated as close to the adc clock pins as possible. for cmos inputs, the clkn pin should be connected to ground, and the cmos clock signal should be connected to clkp. cmos input clock is not recommended above 200 mhz clock frequency. for differential sine wave clock input the amplitude must be at least 0.8 vpp. no additional confguration is needed to set up the clock source format. the quality of the input clock is extremely important for high-speed, high-resolution adcs. the contribu - tion to snr from clock jitter with a full scale signal at a given frequency is shown in equation 1. snr jitter = 20 log (2 ? in ? t ) (1) where fin is the signal frequency, and t is the total rms jitter measured in seconds. the rms jitter is the total of all jitter sources including the clock generation circuitry, clock distribution and internal adc circuitry. for applications where jitter may limit the obtainable performance, it is of utmost importance to limit the clock jitter. this can be obtained by using precise and stable clock references (e.g. crystal oscillators with good jitter specifcations) and make sure the clock dis - tribution is well controlled. it might be advantageous to use analog power and ground planes to ensure low noise on the supplies to all circuitry in the clock distribution. it is of utmost importance to avoid cross - talk between the adc output bits and the clock and between the analog input signal and the clock since such crosstalk often results in harmonic distortion. the jitter performance is improved with reduced rise and fall times of the input clock. hence, optimum jitter performance is obtained with lvds or lvpecl clock with fast edges. cmos and sine wave clock inputs will result in slightly degraded jitter performance. if the clock is generated by other circuitry, it should be re-timed with a low jitter master clock as the last operation before it is applied to the adc clock input. application usage example this section gives an overview on how HMCAD1512 can be used in an application utilizing all active modes with a single clock source. the example assumes that a 1 ghz clock source is applied. a differential clock should be used, and can be generated from a single ended crystal oscillator, using a transformer or balun in conjunction with ac-coupling to convert from single ended to differential signal. start-up initialization the start-up sequence will be as follows: ? apply power ? apply reset (resetn low, then high, or spi com - mand 0x00 0x0001) ? set power down (pd pin high or spi command 0x0f 0x0200) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 28 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter ? set lvds bit clock phase (phase_ddr, regis - ter 0x42)) if other than default must be used (depends on the receiver). ? select operating mode, for instance dual channel mode, and clock divider factor (spi command 0x31 0x0102). ? set active mode (pd pin low or spi command 0x0f 0x0000) ? select analog inputs, for instance input 1 on channel 1 and input 3 on channel 2 (spi com - mands 0x3a 0202 and 0x3b 0808) change mode when changing operational mode, power down must be activated due to internal synchronization routines. a typical mode change will then be like this: ? set power down (pd pin high or spi command 0x0f 0x0200) ? change mode to for example single channel mode (spi command 0x31 0x0001) ? set active mode (pd pin low or spi command 0x0f 0x0000) ? select analog inputs, for instance input 1 (spi commands 0x3a 0202 and 0x3b 0202) table 25 gives an overview of the operational modes in this example and the spi commands to apply for each mode. table 24: overview of operating modes and setup conditions operating mode sampling speed (msps) clock divider factor spi command for mode selection and clock divider single channel 900 1 0x31 0x0001 dual channel 450 2 0x31 0x0102 select analog input when an operational mode is selected, the analog inputs can be changed on-the-fy. to change analog input one merely have to apply the dedicated spi commands. the change will occur instantaneously at the end of each spi command. table 25: example of some analog input selections operating mode signal input selection spi commands single channel ip2/in2 0x3a 1010, 0x3b 1010 dual channel ch1: ip1/in1 0x3a 0404, 0x3b 0808 ch2: ip2/in2 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 29 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter table 26: 7x7 mm qfn 48 pin (lp7) dimensions symbol millimeter inch min typ max min typ max a 0.8 0.9 1 0.031 0.035 0.039 a1 0 0.02 0.05 0 0.0008 0.002 a2 0.2 0.008 b 0.18 0.25 0.3 0.007 0.01 0.012 d 7.0 0 b s c 0.276 bsc d2 5.15 5.3 5.4 0.203 0.209 0.213 l 0.3 0.4 0.5 0.012 0.016 0.02 e 0.50 bsc 0.020 bsc f 0.2 0.008 package information part number package body material lead finish msl [1] package marking [2] HMCAD1512 rohs-compliant low stress injection molded plastic 100% matte sn level 2a had1511 xxxx [1] msl, peak temp: the moisture sensitivity level rating classifed according to the jedec industry standard and to peak solder temperature. [2] proprietary marking xxxx, 4-digit lot number xxxx outline drawing for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com a/d converters - smt 30 HMCAD1512 v01.0812 8-bit, dual-channel 450 ms/s or single-channel 900 ms/s a-to-d converter notes: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com |
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